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New Product: Peter Wolters double-sided silicon wafer polishing handles 22nm node

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Product Briefing Outline: Peter Wolters GmbH, a wholly-owned subsidiary of Novellus Systems has developed an advanced polishing technology for its MicroLine AC 1500-P³ and AC 2000-P³ double-sided silicon wafer polishing (DSP) systems that will meet the lithography requirements for semiconductor device manufacturing at 22nm and beyond.

Problem: With current state-of-the-art semiconductor manufacturers beginning to enter 32nm high-volume manufacturing, leading manufacturers of wafer polishing equipment are already considering the planarity requirements for silicon wafers at the 22nm technology node. At these next generation nodes, extremely tight requirements are being placed on both the shape of the prime wafer and the flatness of its surface. Since semiconductor device structures are patterned using optical lithography, the achievable process window or depth of focus becomes governed by the flatness of the area being exposed by the optical beam. The “degree of silicon wafer local flatness” as measured by the Site Frontside Least Squares Focal Plane Range metric (or SFQR, see Figure 1) defines the acceptable level of silicon wafer surface planarity for use in advanced IC manufacturing. Lithography processes require the SFQR value to be much smaller than the depth of focus. To meet the current needs of 32nm lithography, the SFQR-max value is typically less than 30nm for a site size of 26 mm x 8 mm with an edge exclusion of 2 mm. A double-sided silicon wafer polish is required to achieve low SFQR values at these advanced nodes. Another significant challenge during the polishing step is to control wafer planarity (parallel front and back wafer surfaces) while preventing the pad from rounding the edge of the wafer.

Solution: Peter Wolters has developed new sensor and process control capabilities into its latest polishing systems, allowing the AC-1500 P3 and the AC-2000 P3 to achieve SFQR-max values of less than 20nm —a requirement for 22nm lithography (see Figure 2). Improved front to backside parallelism is achieved using stress-free guidance of the wafer throughout the polish step. The process control enabled by this new technology is claimed to deliver a more homogeneous polishing process with no edge rounding out to 1 mm of edge exclusion. When used for today’s 4Xnm and 3Xnm production, the MicroLine’s flatter wafers are claimed to widen the depth of focus process window, resulting in improved critical dimension control. This larger process window is said to increase patterning yield and lithography productivity through better scanner-to-scanner matching and reduced qualification and set-up time.

Applications: Silicon wafer polishing

Platform: The MicroLine AC 1500-P³ and AC 2000-P³ double-sided silicon wafer polishing (DSP) systems use in-situ data of the temperature and eddy current sensors to adjust the process parameters to match the polishing consumables with the incoming wafer geometry.

Availability: June 2009 onwards.

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