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Product Briefing Outline: Novellus has developed an innovative copper electrochemical process called ‘Suppression-Enhanced Fill’ (SEF) that eliminates defects when scaling to the 32nm technology node. The SEF process utilizes the capabilities of the company's ‘SABRE Extreme’ platform to simultaneously enhance current suppression on the wafer field and within the upper sidewalls of contacts and trenches while permitting copper deposition to initiate rapidly from the bottom of these features.

Problem: Since the advent of copper damascene processing, achieving void-free fill of high aspect ratio interconnect features has been a key challenge for device manufacturers. Shrinking dimensions at each successive technology node have increased the complexity of the copper seed and electroplating processes, and stringent yield and reliability requirements have intensified the focus on reducing defects. Copper interconnect defects can be caused by a multitude of factors, including post-patterning etch residue, discontinuous barrier or seed layers, and inadequate electroplating nucleation and deposition. Overcoming these interconnect scaling challenges is paramount to increasing memory bit density, shrinking chip form factor and enhancing circuit functionality. Device manufacturers need solutions to these problems to enable the next generation of consumer-driven applications such as solid state drives and smart phones.

Solution: For high-volume manufacturing applications at 45nm and beyond, Novellus' advanced copper electrochemical deposition hardware, processes, and chemistries are claimed to provide bottom-up, void-free filling of advanced device structures. The Suppression-Enhanced Fill process eliminates defects and enhances current suppression on the wafer field and within the upper sidewalls of contacts and trenches. Copper deposition from the bottom of the features can then be achieved. In addition, SEF increases fill nucleation density and decreases the possibility of seed dissolution, resulting in copper electrofill that is easier to integrate with today's barrier and seed technologies. Studies have shown that 32nm features filled using the SEF process, resulted in a more robust, void-free fill, according to the company.

Applications: 45nm and below void-free fill of high aspect ratio interconnect features.

Platform: SABRE(R) Extreme platform uses a Novellus, ATMI and Enthone developed chemistries known as ‘ViaForm’ and ‘Extreme Pura.’

Availability: April 2009 onwards.