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New Product: Line edge roughness reduction at 45nm on Applied‚??s Producer APF-e system

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AMATProduct Briefing Outline: Applied Materials has introduced the Applied ‘Producer' ‘APF-e' system for depositing advanced patterning films in less than or equal to 70nm Flash and DRAM memory devices and less than or equal to 45nm Logic applications. According to the company this is a key enhancement to its first-generation APF film providing for greater optical transparency to deliver precise lithographic alignment in thicker (greater than 2,000A) hardmask layers. The APF-e film's are intended to be seen as a cost-effective hardmask technology featuring high selectivity to polysilicon and oxide to enable the key etch patterning steps required for continued geometric scaling

Today's tough patterning challenges require innovative pattern transfer solutions that maximize the lithography process window and improve overall fab economics, especially in high-density chips like Flash and DRAM. Applied's APF-e film is highly selective to polysilicon (6:1) and oxide etching (15:1) and eliminates the line edge roughness associated with photoresist-only schemes, providing much tighter critical dimensional control for improved device performance and yield, according to the company. APF-e technology also eliminates the expensive wet cleaning steps needed by multi-layer resist processes.

Solution: The APF optically engineered patterning film stack combines the CVD-based amorphous carbon APF or APF-e hardmask films with Applied's ‘DARC' films to enable advanced lithography and etching using standard lithography tools. Applied's APF films are already being used in up to seven layers in 70nm Flash memory chips, including shallow trench isolation and sub-40nm gate definition, plus other key applications. Even more layers are likely to be implemented in next-generation devices.

Applications: Lithography and etch patterning of shallow trench isolation (STI), gate, and contact features.

Platform: The Producer platform uses a twin chamber architecture that enables simultaneous processing of up to six wafers.

Availability: July 2007 onwards.

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