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New Product: Invarium reveals ‚??Process and Proximity Compensation‚?Ě software for 65nm layout-to-m

09 February 2006 | By Mark Osborne | Product Briefings > Lithography

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InvariumProduct Briefing Outline: Invarium, Inc has unveiled "DimensionPPC," which it claims to be the industry's first unified, full-chip Process and Proximity Compensation (PPC) product for patterning integrated circuit (IC) layouts at 65 nm and below. Architected from the ground up as a new-generation layout-to-mask solution, DimensionPPC is intended to overcome the deficiencies of today's RET/OPC tools and layout correction techniques for other process effects, from mask through etch. The product has been fab-validated at 65nm during the fourth quarter of 2005. The technology is currently in production deployment at one customer site and is being qualified for production use by five additional leading semiconductor manufacturers.

Problem:
With each successive technology node, patterning becomes more challenging and requires significantly greater help from software to augment hardware and process limitations. Thus far, the industry has coped well with existing RET/OPC tools that were conceived multiple nodes ago. At 90 nm, however, the first serious bottlenecks appeared, necessitating considerable additional efforts by lithography/DFM engineers to extend the current tools to this node. At 65 and 45nm, an entirely new level of analytical capabilities and software rigor is required to achieve the best possible patterning results and efficiently transition from layout completion to volume production. Invarium's DimensionPPC is engineered specifically for these advanced nodes and is built on a technology foundation with a vision to 32nm and EUV lithography.

Solution: DimensionPPC is patterning-process-centric technology. It is comprised of a powerful PPC model and an advanced mask layout synthesis engine. The PPC model is a rigorous, analytical model of the entire patterning process that captures all key process effects and process variations with any significant impact on pattern fidelity, without requiring the creation of multiple models for different process conditions. The model enables an accurate simulation of how an IC layout will be patterned post-etch and across the process window. The mask layout is then optimally synthesized in a single, unified step that embodies RETs and inversions of actual process effects to ultimately produce a mask that delivers the best patterning results on silicon. The product's "correct- by-construction" approach is claimed to cut the cycle time from layout completion to volume production by simplifying the tape-out flow, reducing RET/OPC missteps, and averting needless mask and silicon re-spins. DimensionPPC is designed to reduce overall costs by reducing mask iterations and software investment costs, and eliminating the need for independent OPC verification.

Applications: 65nm and below

Platform: DimensionPPC was architected for high scalability, and runs on standard computer clusters and distributed processors, providing fast turnaround times (TAT) without requiring custom hardware.

Availability: February 2006 onwards.

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