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New Product: ASML’s new TWINSCAN NXT platform has a new planar wafer stage design
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Product Briefing Outline: ASML has improved its TWINSCANTM lithography platform that offers significant improvements in overlay and productivity, enabling the semiconductor industry to continue its roadmap for more advanced and affordable chips. The TWINSCAN NXT platform is suited for emerging double patterning techniques (DPT) which manufacturers need to shrink the smallest chip features by up to 42 percent.
Problem: DPT describes a variety of lithography techniques that involve splitting a complex layer pattern into two (or more) simpler patterns, and exposing them separately to recreate the original layer pattern on the wafer. This allows features to be created on the wafer that are smaller than could be resolved by the scanner in a single exposure. DPT using ArFi lithography is currently seen as the most likely technology for production at 32 nm. The accuracy required to align the multiple patterns places much tighter critical dimension uniformity (CDU) and overlay than the single-exposure techniques used to date. In addition, multiple lithography steps per layer mean ultra-high throughput lithography systems are needed to maintain fab productivity.
Solution: The TWINSCAN NXT platform features a new planar wafer stage design, extending the modular TWINSCAN architecture for multiple generations of ASML lithography machines. The new stage uses a new concept and innovative materials that are considerably lighter than previous generations. This, in combination with an elegant design that reduces overhead, enables high acceleration for shorter positioning (stepping) times. As a result, the platform will initially improve productivity by more than 30 percent, according to the company. In addition, a new positioning measurement system positions the wafer stage even more accurately than in current systems. The resulting overlay improvement of a claimed 50 percent will help manufacturers gain better control of their process so they can produce more good chips per wafer and further shrink transistor sizes.
Applications: Double patterning techniques required for volume production applications at 32nm and below.
Platform: ASML has incorporated lightweight materials into a compact design that results in a reduction in weight of the system by 66%.
Availability: In 2009.