Product Briefing Outline: ASML and its subsidiary Brion Technologies have introduced the ‘LithoTuner’, a new suite of products that integrates computational and wafer lithography to improve semiconductor manufacturability. LithoTuner Pattern Matcher and LithoTuner Pattern Matcher FullChip are designed to enable scanner matching improvements of between 30-70% over current scanner matching techniques. Pattern Matcher has been made available for ‘TWINSCAN’ ArF immersion, ArF dry and KrF DUV lithography systems.
Problem: As feature sizes become ever smaller, the manufacturing challenges increase almost exponentially, putting extremely tight requirements on parameters such as overlay and critical dimension uniformity (CDU). Even the tiniest process variation can have a potentially disastrous effect. Traditionally, lithography tools would be tied to batches and chip designs to control variability, reducing the potential throughput and utilization of expensive lithography tools.
Solution: Pattern Matcher FullChip extends current scanner matching practices by leveraging Brion’s verification engine to identify all the critical patterns across the entire chip that need to be matched. By coupling this computational analysis with an interface to ASML scanners, a comprehensive matching solution is claimed, giving chip makers access to a larger set of tuning adjustments. The additional benefit of this holistic approach is that scanners can be optimized depending on the different chip designs. Scanner matching optimization can now cover the full chip and all customer selected patterns over the entire process window, tuning each scanner in the fab for every product. With a fully tuned fab, lithography engineers can increase system utilization by releasing product dedication to scanners for improved process latitude and a better return on their lithography investments.
Applications: ASML’s ‘TWINSCAN’ ArF immersion, ArF dry and KrF DUV lithography systems.
Platform: Computational lithography is the use of computer modeling to predict, correct, optimize and verify imaging performance of the lithography process over a range of patterns, process, and system conditions. Holistic lithography is the integration of computational and fab lithography to optimize imaging performance from mask design to factory manufacturing.
Availability: First quarter of 2009.