Online information source for semiconductor professionals

Product Briefing Outline: Applied Materials has introduced its ‘Applied Centura Enabler E5’ dielectric etch system that is designed to fabricate 40:1 high aspect ratio contact features at the 32nm node and below for DRAM and Flash memory chips. The Enabler E5 is claimed to achieve >80% bottom-to-top CD ratios across the wafer, and with less than 3nm bowing of the contact sidewall.

Problem: Next-generation Flash and DRAM devices pose a significant challenge for dielectric etch systems since it is very difficult to achieve the global profile control necessary for fabricating high aspect ratio contacts.

Solution: The Applied Centura Enabler Etch is said to incorporate a unique design that results in a highly controllable, multi-application process capability that accommodates all-in-one processing of BEOL dual damascene low-k integration schemes for high-volume production as well as advanced high aspect ratio (HAR) contact structures for FEOL.  Specifically refined for HAR applications at current and future memory technology nodes, the Enabler E5 etches contact aspect ratios exceeding 40:1, with >80% bottom-to-top critical dimension ratios, CD bias non-uniformity of <3nm, and no profile bending. Enabler performs all the steps in a complex integration scheme (e.g., mask open, via, trench, resist strip and residue removal, barrier open) in a single chamber. The resulting stable and repeatable etch performance is due to superior plasma stability over a large pressure/flow operating window. The system operates with plasma on from step to step, which is claimed to provide substantial savings in costs and cycle time by eliminating plasma re-ignition steps. Independent inner and outer wafer temperature tunability, higher-power dual frequency bias, and a modified gas delivery scheme are designed to enhance etch depth capability, improved etch rate and CD bias uniformity as well as large bottom-to-top CD ratio with no profile bending.

Applications: High aspect ratio contact features for 32nm and below DRAM and Flash memory chips.

Platform: Central to the Enabler E5 system’s performance are its unique reactor architecture and precise process control that provide repeatable, uniform vertical profiles at high aspect ratios globally – from edge-to-edge and wafer-to-wafer – addressing a critical yield inhibitor at higher memory densities. The proprietary chamber technology also provides more efficient cleaning, that is claimed to result in 50% longer between-maintenance intervals than any competitive system.

Availability: December 2008 onwards.