Online information source for semiconductor professionals

News > Wafer Processing

TSMC starts customer 65nm prototype wafer shuttle service

05 October 2005 | Wafer Processing
Taiwan Semiconductor Manufacturing Company has completed the first of three CyberShuttle prototype production runs for its 65nm process technology. According to the Taiwanese foundry, five customers' designs and multiple 3rd party IP designs are on the first shuttle. Fabless companies taking part included Altera and Broadcom. On the IDM side, Freescale has also taken part. TSMC also reiterated that the wafer shuttle service contained both a low power process and a high performance process. Beginning in 2006, TSMC will launch additional 65nm shuttles every other month, enabling customers and EDA, IP and library suppliers to prototype and qualify 65nm designs. Read more >>

Jazz juggles with low cost 130nm process

05 October 2005 | Wafer Processing
Jazz Semiconductor, a niche wafer foundry, is to start offering a 130nm process using aluminum rather than copper for interconnects to enable key analog and RF functions to be integrated as low power logic with high-performance analog and RF circuitry. "RF System on Chip integration for low-cost wireless is a critical component of the growing portable and connected electronics markets. Jazz Semiconductor's 0.13 micron process platform provides an efficient option, enabling RF System on Chip integration," said Joanne Itow, managing director, Semico Research. "The follow-on 0.13 micron SiGe version will further enable circuit designers to achieve higher levels of integration at higher speeds." Read more >>

AmberWave claims more strained silicon patent infringements against Intel

29 September 2005 | Wafer Processing
AmberWave Systems Corporation has stated that a newly awarded U.S Patent covering its strained silicon process IP is being used by Intel Corporation without licensing consent. Read more >>

Infineon and Nanya carry-on joint DRAM process development

29 September 2005 | Wafer Processing
Infineon Technologies AG and Nanya Technology Corporation are to continue their joint process development program beyond the current agreement that covers 90nm and 70nm production processes. Read more >>

SEMATECH offers hope for 45nm low-k target

28 September 2005 | Wafer Processing
In a paper presented at the Advanced Metalization Conference (AMC) at Colorado Springs, CO, SEMATECH and Rohm and Haas Electronic Materials researchers revealed work being carried out to provide a k-effective (keff) value of 2.5 in dual damascene work flows targeted by the ITRS roadmap for the 45nm node. Read more >>

Tool Orders: AMD repeats implant order with Axcelis

28 September 2005 | Wafer Processing
The system will be shipped during September to AMD's Fab 36, a 300mm fab in Dresden, Germany. The implanter will be used for volume production of advanced transistors using 65nm and 45nm device technologies. AMD was the first company to purchase the new single wafer platform, according to Axcelis. Read more >>

EVENT: AVS Announces 7th International Conference on Microelectronics and Interfaces March 6-8, 2006

23 September 2005 | Wafer Processing
Co-sponsored by SEMATECH and the Advanced Materials Research Center New York and Austin, TX (Sept. 23, 2005) -The International Conference on Microelectronics and Interfaces 2006 (ICMI '06) is continuing its mission to provide a unique opportunity for industrial, government, and academics scientists and engineers working in the areas of microelectronics devices, processing, and process integration to gather and exchange ideas regarding the challenges of nanodevice fabrication. The event will held at the Omni Hotel, Austin-Downtown, Austin, TX Read more >>

New Product: Applied Materials reveals FEOL pre-clean chamber

21 September 2005 | Wafer Processing
Applied Materials, has announced a new process and chamber to tackle transistor contact engineering issues at the 65nm node and below. Applied's  "Siconi" pre-clean process replaces conventional plasma-based sputter etch technology with a dry, chemical process removes oxidized silicon under high vacuum and is being offered as a module on the Applied Endura ALPS Ni PVD system. Read more >>

Is TI‚??s high k on the highway?

19 September 2005 | Wafer Processing
Texas Instruments is to migrate "SmartReflex" leakage power technologies to 65nm devices, the company said in a press statement. Some of the technology was first introduced for some of TI's 90nm devices in the last 18 months and was positioned then as a work around for leakage issues experienced at that node. However, the wording of today's release give the strong impression that the technology has been further developed to assist the company in providing power consumption gains for its next generation of products. TI states that "has solved the 65nm leakage power challenge for mobile devices with its "SmartReflex" power and performance management technologies." Read more >>

Tool Order: Major North American IDM selects Semitool‚??s Raider SP cleaning system

16 September 2005 | Wafer Processing
Major North American IDM has selected for one of its fabs, Semitools Raider SP cleaning system for 65nm production and will be deployed in FEOL cleaning applications. The single wafer platform has already been delivered. The Semitool Raider is the latest generation single-wafer tool that joins the company's install base of more than 2800 single-wafer chambers installed in more than 500 single wafer tools. Read more >>