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A Japanese 300mm logic fab has placed a multi-million dollar, multi-tool order for Therma-Wave, Inc's Opti-Probe 7341XP thin-film and critical dimension metrology systems. The tools will be used to support front end as well as back end 300mm logic device manufacturing processes at the 90nm node as part of a transition to copper based production. Read more >>

Taiwan foundry UMC has put in a follow-on order for Axcelis Technologies' RadiantStrip 320Lk photoresist dry strip and cleaning system. The RadiantStrip 320Lk system has become UMC's "process tool of record". The system will ship to UMC's Fab 12A in Tainan, Taiwan, by the end of 2005. Read more >>

Freescale Semiconductor plans to enter into 65nm IC prototyping in November of this year. Work will be carried out at the Crolles2 joint development facility with STM and Philips in Crolles, France. "We have addressed many of the industry's widely reported challenges with 90-nm and are applying our expertise to the next generations of technology," said Freescale's Chief Technology Officer Dr. Claudine Simson. "Our achievements at 90-nm over the past year set the stage for successful 65-nm prototyping, which we will begin in November." Read more >>

Oki Electric Industry Co., Ltd has presented details of its fully depleted SOI process that it claims reduces standby leakage current by over 90 percent yet retains performance figures of its previous SOI devices. This was achieved by using a transistor that had a non-doped body and non-overlap type SOI structure. The device was revealed during 2005 SOI Conference in Honolulu, Hawaii. Read more >>

Taiwan Semiconductor Manufacturing Company has completed the first of three CyberShuttle prototype production runs for its 65nm process technology. According to the Taiwanese foundry, five customers' designs and multiple 3rd party IP designs are on the first shuttle. Fabless companies taking part included Altera and Broadcom. On the IDM side, Freescale has also taken part. TSMC also reiterated that the wafer shuttle service contained both a low power process and a high performance process. Beginning in 2006, TSMC will launch additional 65nm shuttles every other month, enabling customers and EDA, IP and library suppliers to prototype and qualify 65nm designs. Read more >>

Jazz Semiconductor, a niche wafer foundry, is to start offering a 130nm process using aluminum rather than copper for interconnects to enable key analog and RF functions to be integrated as low power logic with high-performance analog and RF circuitry. "RF System on Chip integration for low-cost wireless is a critical component of the growing portable and connected electronics markets. Jazz Semiconductor's 0.13 micron process platform provides an efficient option, enabling RF System on Chip integration," said Joanne Itow, managing director, Semico Research. "The follow-on 0.13 micron SiGe version will further enable circuit designers to achieve higher levels of integration at higher speeds." Read more >>

AmberWave Systems Corporation has stated that a newly awarded U.S Patent covering its strained silicon process IP is being used by Intel Corporation without licensing consent. Read more >>

Infineon Technologies AG and Nanya Technology Corporation are to continue their joint process development program beyond the current agreement that covers 90nm and 70nm production processes. Read more >>

In a paper presented at the Advanced Metalization Conference (AMC) at Colorado Springs, CO, SEMATECH and Rohm and Haas Electronic Materials researchers revealed work being carried out to provide a k-effective (keff) value of 2.5 in dual damascene work flows targeted by the ITRS roadmap for the 45nm node. Read more >>

The system will be shipped during September to AMD's Fab 36, a 300mm fab in Dresden, Germany. The implanter will be used for volume production of advanced transistors using 65nm and 45nm device technologies. AMD was the first company to purchase the new single wafer platform, according to Axcelis. Read more >>