EV Group and Brewer Science are to offer customers in Taiwan and the Asia-Pacific Region access to both companies technology and process offerings for the development and implementation of through-silicon via (TSV) technology for 3D IC packaging. As part of the continued collaboration, EVG's 500 series wafer bonding system was integrated in the applications lab in Taiwan in December 2008. The move is also expected to facilitate training of customer’s engineers in TSV processes.
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FSI International has said it has received an order from a major semiconductor manufacturer that had been evaluating its new ‘ORION’ single wafer cleaning platform, since May, 2008. The system employs a unique closed-chamber design that is claimed to tackle challenging cleaning issues at the 32nm and below. The new system was officially launched in November, 2008.
Tokyo Electron Limited (TEL) has signed a licensing agreement with ASM International covering the Dutch firm's currently filed and issued Atomic Layer Deposition (ALD) patents. TEL plans to use the license to offer batch reactor processes to its customers for sub-32nm applications. TEL’s main single wafer CVD tool is based on the Trias platform.
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Toshiba Corp. has revealed its new cost-effective 32nm CMOS platform technology, that is claimed to halve the cost per function compared to that of 45nm technology. The new technology, claimed to offer higher density and improved performance, was achieved via application of advanced single exposure lithography and gate-first HKMG process technology. It is claimed to enable a 0.124μm2 SRAM cell and a gate density of 3,650 gate/mm2, the smallest SRAM cell in the 32nm generation to date.
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Mattson Technology, Inc. has revealed that it has shipped one of its dual-chamber 300mm rapid thermal processing (RTP) systems to Hynix Semiconductor, Inc.'s R3 memory R&D facility in Korea. The system is currently being installed in Hynix’s facility, will aid in meeting the company’s increased process requirements for high-volume chip manufacturing through the 45nm technology node and beyond.
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DALSA semiconductor has said that tests undertaken on the eG ViaCoat process from Alchimer S.A. enabled the MEMS device producer to fabricate conformal copper seed layers on through-silicon via structures (TSVs), while overcoming the inherent problems of reentrant TSV, using the Bosch deep reactive ion etching (DRIE) processes.
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Tokyo Electron Limited (TEL) has cancelled the planned groundbreaking of a new equipment assembly plant in Taiwa-cho, Miyagi Prefecture, due to the drop in capital equipment spending in the semiconductor industry and poor industry dynamics expected in 2009. Originally, TEL planned to start construction in April 2009, with completion the same month the following year.
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Nemotek Technologie, a wafer-level cameras, packaging and optics company, has ordered Eyelit Inc.’s manufacturing suite for applications in production support in Nemotek’s new wafer fab in Rabat, Morocco. The order is the second received this month by Eyelit, having only a few weeks ago announced an order from SiCrystal.
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