Online information source for semiconductor professionals

The University of Notre Dame, Notre Dame, Indiana, has purchased Vistec’s EBPG5200 e-beam lithography system that is equipped with a modified platform that supports full exposure of substrates to a maximum size of 200mm. The University will use the system for research on new electronic, optoelectronic and magnetic device concepts and associated architectures at Notre Dame’s Center for Nano Science and Technology and the Notre Dame Nanofabrication Facility (NDNF). Read more >>

A large Asian-based IC manufacturer are installed Cymer’s XLR 600ix field-selectable 60 watt–90 watt, immersion light source into a Nikon scanner system, making it the first immersion light source of this kind to be installed. Cymer also claimed that all of the industry’s immersion double patterning light source selections in 2009 have been awarded to the company. Read more >>

An important step in bringing e-Beam maskless lithography to the fab floor could be in the making with news that MAPPER’s massively parallel electron beam platform is to be shipped to CEA-Leti, kicking-off a its three-year IMAGINE program to make the technology ready for IC production at the 22nm node and beyond. Read more >>

Cymer, Inc. has shipped the world’s first fully integrated laser-produced plasma (LPP) Extreme Ultraviolet (EUV) lithography source tool to ASML in Veldhoven, The Netherlands where it will support integration and testing of next generation EUV lithography scanners. This purchase is the first of many in an agreed multi-unit purchase deal. Read more >>

Loss-making photomask manufacturer Photronics is closing its only mask shop in China with the loss of approximately 75 jobs. The move is part of Photronics' efforts to lower its operational breakeven point. Mask shops in other Asian locations including Korea, Singapore and two sites in Taiwan will supply customers in China, the company said. In October 2008, Photronics announced the closure of its mask shop in the UK and recently re-negotiated its lease agreement at its joint venture mask shop with Micron Technology.

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A group of companies are to collaborate on improving design for mask manufacturing (DFMM) by breaking the barriers that have traditionally separated IC designers from mask shop engineers. Under Crystal, a European collaborative R&D program sponsored by the Cluster for Application and Technology Research in Europe on NanoElectronics (CATRENE), Satin IP Technologies SAS, Toppan Photomasks France SAS and XYALIS SaRL will also work to make mask manufacturing a more efficient and less iterative process. Read more >>

SEMATECH has accepted Veeco Instruments' ‘InSight’ 3D Atomic Force Microscope for non-destructive reference metrology for critical dimension (CD), overlay and contour, as well as 3D characterization of EUVL resist features. SEMATECH’s Metrology Program is located at the College of Nanoscale Science and Engineering’s (CNSE) Albany NanoTech Complex. Read more >>

A more purposeful and deliberate move by TSMC to push the semiconductor industry towards the adoption of e-beam technology for volume production was made with a new technology development agreement with CEA-Leti. The French semiconductor research institute is to work with TSMC to push Dutch firm Mappper Lithography’s multi-beam maskless technology into the mainstream. The three-year program includes tool assessment, patterning and process integration, data handling, prototyping and cost analysis. Read more >>

Dai Nippon Printing (DNP), producer of semiconductor photomasks, and Molecular Imprints, producer of nanopatterning systems and solutions, are collaborating to speed production of nanoimprint lithography for high-volume semiconductor device manufacturing. DNP is the official provider of funds and support for Molecular Imprints to develop a new mask replication platform aimed at lowering the cost of imprint masks. Read more >>

To maximise yield and limit IC design costs, TSMC is providing access to its tool chain and process models for its 28nm process, in an effort to help designers limit hotspot correction work for lithography limitations. This is a move away from abstracted models, which at these geometries lose information in the translation process, forcing designers to overcompensate for lithography hotspots that take time and increase surface area. Read more >>