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UMC looks at hybrid gate-first and gate-last techniques

10 December 2009 | By Mark Osborne | News > Wafer Processing

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Taking a hybrid approach to high-k/metal-gate (HK/MG) technology for the 28nm node, UMC has presented a paper at IEDM that is claimed to combine the benefits of both gate-first and gate-last processing techniques. UMC claims that this approach delivers 30% enhanced transistor performance compared to a gate-first only process.

"The spirit of innovation is always a key factor when developing advanced technologies," said Mr. S.C. Chien, vice president of Advanced Technology Development at UMC. "This published work demonstrates UMC's ability to conceive and develop alternative solution paths, leveraging in-depth learning of existing HK/MG process options to respond to today's rising demand for cutting-edge products and applications."

For gate-first, the HK/MG is inserted before the gate is patterned (formed). For 'gate-last' or 'replacement metal gate', MG is 'filled in' after a polysilicon dummy gate is formed and then removed.

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