TSMC has detailed further process developments for its low-power process options for the 28nm node. The major foundry will use a gate-last approach for its high-k metal gate 28nm transistors, which will enter ‘risk’ production in the third quarter of 2010. This follows the HKMG high performance process by one quarter and the low power (LP) silicon oxynitride (SiON) process by two quarters.
"We developed a gate-last approach for TSMC's 28nm high-k metal gate family that is superior in terms of transistor characteristics, high end and low end performance upside, and manufacturability," said Dr. Jack Sun, vice president, Research and Development, TSMC.
TSMC said that risk production for the 28nm low power SiON process was scheduled for the end of first quarter of 2010, while risk production for the 28nm HP process was expected at the end of second quarter, 2010.
The foundry also touted its success of achieving what it claims is the first foundry to achieve 28nm functional 64Mb SRAM yield, as well as across all three 28nm node offerings.
“It is particularly noteworthy because this achievement demonstrates the manufacturing benefits of the gate-last approach that we developed for the two TSMC 28nm high-k metal gate processes,” noted Dr. Sun.