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TSMC starts 40nm GPU production for AMD
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TSMC has said that the initial production ramp of AMD GPU’s using its 40nm node general purpose process technology has started. The main production ramp is expected in 2009, including other devices and customers, the foundry said. TSMC said that both its 40nm General Purpose (G) and Low Power (LP) process technology versions had begun ramping.
"We view 40nm as an important process node for the cost-effective development of graphics chips and other devices, especially in 2009. This is another example of a long and successful history of AMD and TSMC ramping leading edge processes," said Rick Bergman, Senior Vice-President & General Manager, AMD Graphics Products Group.
“Today designers are faced with the challenge of increasing the functionality of their product while not increasing power consumption. By rolling out the industry’s most advanced programmable logic devices at 40nm, we are enabling designers to quickly achieve new levels of integration and innovation, while staying within their power budgets,” said Bill Hata, Altera senior vice president of Worldwide Operations and Engineering.
"High-performance GPUs are only continuing to grow in importance for a variety of industries," said Debora Shoquist, NVIDIA senior vice president of Operations. "The advantages that TSMC's 40nm G process provides to designing a GPU will allow us to continue pushing the limits of what’s currently possible.”
“While timed to respond to the technical requirements of our broad customer base, the two processes are clearly the right manufacturing processes at the right time and can help the semiconductor industry, and conceivably other portions of the global economy, to innovate out of the current downturn,” said Jason Chen, Vice President, Worldwide Sales & Marketing, TSMC.
The 40G process is claimed to be up to 30 percent faster than TSMC’s 65nm GP process at the same leakage, or up to 70 percent lower leakage at the same speed. TSMC claims that its 40G and 40LP processes offer designers up to a 2.35 times raw gate density improvement over the 65nm node. The 40nm process also features an SRAM cell size, 0.242um2.