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TSMC has said that it will offer a performance-driven general purpose
(40G) 40nm process technology and a 40nm power-efficient low power
(40LP) process with the CyberShuttle prototyping available in April,
June, August, October and December this year. Apparently, 200 blocks
have already been processed on multi-project wafer runs for certain
customers, TSMC said.
"Our design flow can take designs started at 45nm and target it
toward the advantages of 40nm," said John Wei, Senior Director of
Advanced Technology Marketing at TSMC. "A lot of TSMC development work
has gone into ensuring that this transition is truly transparent.
Designers need only concentrate on achieving their performance
objectives."
TSMC said that the transition from 45nm to 40nm low
power technology reduces power scaling by up to 15 percent. The
processes are a direct shrink of TSMC’s 45nm offering, which includes
low-k dielectrics, strain engineering and immersion lithography but not
high-k and metal gates.