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TSMC readies for double patterning at the 20nm node

26 May 2011 | By Mark Osborne | News > Lithography

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At the upcoming Design Automation Conference (DAC) in San Diego California, TSMC is to showcase its 20nm node ‘Transparent Double Patterning’ design solution for the first time, which is a key part of the on-going build up of 20nm design capability within the Open Innovation Platform. The foundry is also detailing Reference Flow 12.0, which features various enhancements for the 28nm node.

 “TSMC customers can immediately take advantage of our 28nm advanced technology and manufacturing capacity while preparing for 20nm in the near future,” said Cliff Hou, TSMC Senior Director, Design and Technology Platform.  “We have enabled customers to achieve their product design goals by closely collaborating with our EDA and IP partners to deliver a solid 28nm design ecosystem.  In addition, the introduction of Reference Flow 12.0 and AMS Reference Flow 2.0 address critical design issues for the next generation of 28nm and 20nm applications.”

TSMC noted that the 20nm node is the first process node where the metal pitch is beyond the lithographic capabilities of existing exposure systems. The use of double patterning is therefore required.  

According to TSMC its Transparent Double Patterning solution enables system and chip designers to migrate to the 20nm node without any modifications to their current design methodologies or flows. The technology is also being delivered to EDA partners and certified for delivery in their commercial products, TSMC said.

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