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TSMC pushes poly usage to 28nm

18 June 2009 | By Mark Osborne | News > Wafer Processing

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Highlighting the conservative and cost sensitive nature of many foundry customers, TSMC is to extend the use of Silicon Oxynitride (SiON)/poly usage beyond 32nm with a dual/triple gate oxide process for low power applications at its 28nm designated node. Details were presented at the 2009 Symposia on VLSI Technology and Circuits in Kyoto, Japan. TSMC expects to offer the process for production in 2010.

Low standby and low operating power transistors using SiON were optimised with strain engineering and aggressive oxide thickness that was claimed to provide up to 25-40% speed improvement or 30-50% active power reduction over prior 45nm technology offerings by the foundry. Other characteristics from this technology include high density and low Vcc_min 6-T SRAM cells, low leakage transistors, conventional analog/RF/electrical fuse components and low-RC Cu-low-k interconnect.

“This development was achieved through close collaboration with customers who are pushing their own boundaries of new applications requiring 28nm technology,” said Dr. Jack Sun, Vice President R&D at TSMC. “We continue this quest to support the most advanced applications being designed by the innovators in the semiconductor industry.”

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