A more purposeful and deliberate move by TSMC to push the semiconductor industry towards the adoption of e-beam technology for volume production was made with a new technology development agreement with CEA-Leti. The French semiconductor research institute is to work with TSMC to push Dutch firm Mappper Lithography’s multi-beam maskless technology into the mainstream. The three-year program includes tool assessment, patterning and process integration, data handling, prototyping and cost analysis.
“TSMC is always pushing for cost-effective lithography and the development of maskless lithography is one of the potential solutions. We have already announced the joint steps with Mapper to explore multiple e-beam lithography for IC manufacturing at 22 nanometer node and beyond,” said TSMC’s VP of R&D, Jack Sun. “By joining the IMAGINE program at CEA-Leti, we intend to federate the semiconductor industry around this technology and accelerate its development and introduction for IC manufacturing.”
In December, 2008, CEA-Leti announced it would purchase a direct-write lithography system from Mapper Lithography for a new program dubbed IMAGINE. TSMC is now joining that program, having purchased a tool from Mapper earlier last year, though delivery was not expected until the second half of 2009.
“Lithography is a major challenge for the industry. A maskless approach can offer flexibility and gain in cost of ownership. Together with MAPPER, we see a route towards industrial throughput,” said Leti’s CEO, Laurent Malier. “Having TSMC on board the IMAGINE program is pivotal and will strengthen the assessment towards manufacturing. It shows the commitment in the technology from the industry and will take maskless lithography to the next step in the development that is required to make it a viable solution for 22-nm manufacturing.”
TSMC’s lithography expert, Burn Lin has persistently raised concerns over the viability of many Next Generation Lithography (NGL) technologies, such as imprint and EUV, preferring to directly support maskless lithography in the hope that throughput issues could be overcome to realistically produce approximately 10wph from a tool with a below US$10 million price tag.
Teaming with CEA-Leti is a further move by TSMC to push the pace of development for this technology and that of Mapper’s tool in particular. Foundries and ASIC producers have long been concerned that the cost of EUV and low throughput compared to conventional DUV technology would not be economically viable for low-volume IC device fabrication.