New interoperable electronic design automation (EDA) technology files have been made available by TSMC for its 65nm, 40nm and 28nm process nodes, which include interoperable process design kit (iPDK), interoperable design rule check (iDRC), layout-versus-schematic (iLVS), and interoperable interconnect extraction (iRCX). The kits are developed and jointly validated with TSMC's EDA partners as part of its Open Innovation Platform.
"TSMC collaborates with multiple EDA vendors to create and validate interoperable EDA formats that accelerate data delivery and ensure the integrity and accuracy of advanced process technology data," said ST Juang, senior director of Design Infrastructure Marketing at TSMC. "The latest version of the iPDK, iDRC, iLVS, and iRCX technology files are production design ready and incorporating the valuable feedback we received from customers and ecosystem partners during the beta test period. The new unified EDA data format provides designers the ability to select qualified EDA tools that match their design needs, improve compliance with TSMC processes, and ensure design accuracy for first-time silicon success."
TSMC developed its first 40nm iDRC/iLVS in collaboration with development partners Mentor and Synopsys as well as QA/validation partners Magma and Cadence.
TSMC also developed its first 65nm iPDK in collaboration with Synopsys and Ciranova as development partners in addition to QA/validation partners Magma and Springsoft.