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TSMC goes directly to 20nm, bypasses 22nm node

14 April 2010 | By Mark Osborne | News > Wafer Processing

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Due to increased competition at next-generation process nodes, especially with the emergence of Globalfoundries as a serious competitor, TSMC said at its 2010 Technology Symposium that it would be skipping the 22nm node and simply offer a 20nm process. The technology will be based on a planar process with enhanced high-K metal gate, novel strained silicon, and low-resistance copper Ultra-Low-K interconnects. TSMC reiterated that it expects to enter 20nm risk production in the second half of 2012.

"We have reached a point in advanced technology development where we need to be actively concerned about the ROI of advanced technology. We also need to broaden our thinking beyond the process technology barriers that are inherent in every new node," commented Dr. Shang-yi Chiang, TSMC Senior Vice President, Research & Development. "Collaborative and co-optimized innovation is required to overcome the technological and economic challenges."

TSMC also noted that the decision to introduce a 20nm process was ‘value driven to make advanced technology a more viable alternative for its customers.’ The foundry said that the move is based on the capability of innovative patterning technology and layout design methodologies required at these advanced technology nodes.

However in regards to patterning technology it is highly unlikely to be referencing EUV lithography, doubtful at this stage to be e-beam lithography and more likely due to continued improvements in 193nm immersion lithography.

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