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Toshiba illustrates cost-effective 32nm CMOS platform technology

18 December 2008 | By Síle Mc Mahon | News > Wafer Processing

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ToshibaToshiba Corp. has revealed its new cost-effective 32nm CMOS platform technology, that is claimed to halve the cost per function compared to that of 45nm technology. The new technology, claimed to offer higher density and improved performance, was achieved via application of advanced single exposure lithography and gate-first HKMG process technology. It is claimed to enable a 0.124μm2 SRAM cell and a gate density of 3,650 gate/mm2, the smallest SRAM cell in the 32nm generation to date.

The platform technology is based on a 32nm process technology, developed in a collaborative move by Toshiba and NEC Electronics Corporation. The work illustrated the transistor performance boost achieved through application of a metal gate/high-K as well as the reduction in threshold voltage mismatch. The layout optimization utilized a bent-shaped type cell, which further decreased threshold voltage mismatch.

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