Online information source for semiconductor professionals

Toshiba and Ponte team on via and contact etch DFM project

31 March 2008 | By Síle Mc Mahon | News > Lithography

Popular articles

New Product: Applied Materials new EUV reticle etch system provides nanometer-level accuracy - 19 September 2011

Oberai discusses Magma’s move into solar PV yield management space - 29 August 2008

‚??Velocity‚?? the new buzzword in Intel‚??s PQS annual awards - 12 April 2012

Applied Materials adds Jim Rogers to Board of Directors - 29 April 2008

New Product: ASML Brion‚??s Tachyon MB-SRAF enables OPC-like compute times - 19 September 2011

ToshibaToshiba and Ponte Solutions are to collaborate on a via and contact etch DFM project that is designed to cut new process/node ramp times by reducing the need to run larger numbers of test wafers. 

"Our agreement with Ponte will allow us to deliver a more robust and high-quality solution to our wafer fabs," said Seiji Onoue, Senior Research Scientist, Process Research Center, Corporate Manufacturing Engineering Center, Toshiba Corporation. "Working with Ponte on the current via and contact etch project, we have been able to extend our analysis beyond standard TCAD environments, making Ponte an essential success partner for us."

"Ponte's physics-based models can predict process variability based on limited process information, so fabs don't need to run large numbers of experimental wafers to tune their processes, leading to faster and cheaper process development," said Ara Markosian, Ponte Solutions CTO. "These models fill the gap between the TCAD environment, traditionally used by R&D teams, and the chip-level environment that designers work in, thus offering a bridge between design and manufacturing teams."

Ponte said that a successful project would result in Toshiba gaining improved prediction levels of design-induced etch rate and CD variations that would aid yields and boost ramp rates.

Related articles

GSMC ‚?? Quality first in the PRC - 01 September 2003

Amkor to purchase Toshiba‚??s Malaysian IC assembly and test operations - 30 September 2011

In Situ Single Chamber Processing: A Proven Capability for Dielectric Etch Processes - 01 March 2002

Using polymer deposition to control contact hole distortion at ‚?§65nm - 01 September 2006

Toshiba continues with 30% NAND flash production reduction - 27 April 2009

Reader comments

No comments yet!

Post your comment

Please enter the word you see in the image below: