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Toshiba and NEC develop high-density MRAM

04 February 2005 | By Syanne Olson | News > Wafer Processing

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Toshiba Corporation and NEC Corporation announced two key advancements toward development of a magnetoresistive random access memory, at the International Electron Devices Meeting (IEDM) 2004 in San Francisco, USA.

The two companies announced a new cell design that halves power consumption during data writes and cuts writing errors, and a novel MRAM architecture with high speed characteristics and a performance that will support development of high-density devices.

While MRAM show great promise for application in mobile information equipment, cell size and power consumption must be reduced, and no loss of operating speed achieved, before commercial application is possible. NEC and Toshiba reduced write current by developing a new shape for the magnetic tunneling junction (MTJ) that stores information in the cell. The MTJ shape is similar to the standard rectangular shape, but with arc-shaped bulges on both sides, in the middle of the longer length. Seen from above, the outline of the shape resembles a coin placed on a rectangle. With this new design, write current is approximately half that of present MRAM, and writing errors are reduced, even if there is some fluctuation in the switching characteristics of each memory cell.

Toshiba and NEC have also developed highly promising new cell architecture. Research to date has produced two basic proposals on MRAM cell structure. The first of these couples each cell with a transistor, which advances read times, but at a cost in increased cell size. The second, the cross point (CP) structure, removes the transistor from each individual cell, a move that  reduces cell size, but read access time gets longer and read errors occur due to generation of sneak current, the tendency of current to be directed to the unselected cell. Toshiba and NEC have realized a high-speed CP cell structure that uses one transistor to control four cells. This achieves a cell that is the same size as a standard DRAM cell and conventional CP cell, and much smaller than an MRAM cell with transistor.

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