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Tool Order: TEL supplies TSV RIE system to SEMATECH

29 October 2008 | By Mark Osborne | News > Wafer Processing

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300 mm ‘Telius’ SP UD systemTokyo Electron Limited (TEL) has supplied a 300 mm ‘Telius’ SP UD system for through-silicon-via (TSV) etch applications to SEMATECH's 3D R&D center at CNSE's Albany NanoTech Complex in Albany, NY. The Telius SP UD system has the versatility to investigate various chemistries to etch vias ranging from sub 1 micron to tens of microns wide.

"TEL was the first associate member of the 3D program and has been a valued partner of the Interconnect division for many years.  Given their experience in deep silicon etching, we are very pleased to partner with TEL on this critical aspect of developing 3D interconnects," said John Warlaumont, SEMATECH's vice president of advanced technology.  "Leveraging CNSE's pilot line to establish a 300 mm 3D R&D center is a unique opportunity.  It allows our researchers to address the technical and manufacturability issues of creating 3D interconnects within a state-of-the-art CMOS environment."

Masayuki Tomoyasu, senior vice president and chief engineer for TEL, added, "The integration of TEL's leading-edge 3D tools with SEMATECH's R&D capabilities and know-how will bring significant benefits to our semiconductor customers by refining our processes for TSV etch development."

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