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Synopsys and Mattson join forces on TCAD process simulation for CMOS processes

16 July 2008 | By Síle Mc Mahon | News > Wafer Processing

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CMOS technology scaling requires constant review of techniques in order to adhere to ITRS requirements for junction depth and sheet resistance in the source and drain extensions of CMOS transistors. TCAD tools specifically-calibrated models are vital to further development and optimization of the flash annealing process, according to the companies.

"Process technologies are increasingly complex and costly to develop, and therefore TCAD tools with models calibrated to specific process conditions are very important to guide experimentation and process optimization," said Howard Ko, Senior Vice President and General Manager of the Silicon Engineering Group at Synopsys. "Collaborations with leading equipment vendors such as Mattson Technology are a critical component of our strategy to deliver advanced and accurate TCAD tools to the market."

By Síle Mc Mahon

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