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SRC and selected Universities to form 3D packaging R&D centre

26 January 2009 | By Mark Osborne | News > Wafer Processing

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The Semiconductor Research Corporation (SRC) in collaboration with a group of universities that include Georgia Tech, Harvard and Singapore’s Nanyang Technological University are to work on new semiconductor packaging technologies that include a major focus on 3D technologies with US$2.5 million in funding. The joint research will be carried out at a new Interconnect and Packaging Center (IPC), based at Georgia Tech. The IPC will be based in the new Marcus Nanotechnology Building at Georgia Tech.The Semiconductor Research Corporation (SRC) in collaboration with a group of universities that include Georgia Tech, Harvard and Singapore’s Nanyang Technological University are to work on new semiconductor packaging technologies that include a major focus on 3D technologies with US$2.5 million in funding. The joint research will be carried out at a new Interconnect and Packaging Center (IPC), based at Georgia Tech. The IPC will be based in the new Marcus Nanotechnology Building at Georgia Tech.

“Transistors have made enormous progress in speed, performance, and miniaturization, which places greater demand on the electrical connections between transistors, and between individual chips. The interconnect and packaging challenges are greater today than ever,” said Dr. Paul Kohl, director for the IPC. “Georgia Tech has been a leader in creating new interconnect and packaging technologies for integrated circuits and we’re very pleased to partner with SRC in launching the IPC.” International Research Effort for Interconnect and Packaging to Slash Chip Footprint by 10X, Will Be Launched at Georgia Tech.

The Interconnect and Packaging Center receives an annual funding of US$820,000 with SRC providing US$500,000 per year to IPC for three years. The State of Georgia is providing $320,000 for each of three years. The IPC will be based in the new Marcus Nanotechnology Building at Georgia Tech.

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