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The Soitec Group has completed development and qualification of its 300mm ultra-thin SOI (UTSOI) wafer platform for use in supporting fully-depleted device applications on the industry’s CMOS roadmaps for 22nm and beyond. The system is now ready to support mainstream ramp-up of fully depleted applications at the 22nm node, delivering a film thickness uniformity control of ± 5Å.

The UTSOI platform, which was introduced last year, has been undergoing process optimizations and customer qualifications that now enable customers to tailor the final SOI substrate to specific parameters. The company can now manufacture SOI with extremely thin top-layer silicon (20nm) to a thickness uniformity tolerance of ± 5Å in high volume with high yields.
 
 “On fully depleted SOI, we’ve demonstrated 25nm high-k metal-gate devices with matching characteristics far superior to those obtained on bulk silicon,” reported Dr. Olivier Faynot, Director of Advanced SOI technologies Development at CEA-Leti. “As it eliminates the need to dope the channel region, FD SOI solves threshold voltage (V_t) variability challenges at current and future nodes, while maintaining excellent I_on and I_off characteristics and drastically reducing gate leakage current. With this uniform ultra-thin film SOI substrate, Soitec is delivering a solution for substantially improving V_t control of the CMOS device.”