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Soitec teams with IBM on 22nm and beyond wafer-level 3D integration technology

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SOITECSOI substrate provider The Soitec Group has entered into a collaborative agreement with IBM for the development of 22nm-and-beyond silicon wafer substrates and bonding techniques. The study will enable the development of wafer-level 3D integration technology for next-generation ICs.

Building on the companies’ existing working relationship that has seen them collaborate on substrate design and specifications for 15 years, this new effort is geared toward the development of highly flexible and cost-effective solutions for wafer-to-wafer stacking, a technique that yields ICs more quickly and with better performance.

IBM's 3D integration effort will be complemented by Soitec’s Smart Stacking technology. Soitec has developed various wafer-level bonding techniques, including oxide-to-oxide and metal-to-metal molecular bonding, which was developed in collaboration with CEA/Leti (the Electronics and Information Technology Laboratory of the of the French Atomic Energy Commission).
"This collaboration with Soitec is another step in IBM’s drive to accelerate 3D integration technology, and reinforces the expanding IBM ecosystem of leading companies and research organizations that are working together to achieve significant advances in semiconductor and packaging technology," said Dr. Gary Patton, VP, Semiconductor Research and Development Center, IBM. "Through these collaborations, IBM intends to accelerate the development of emerging 3D integration technology and demonstrate the possibilities of achieving higher circuit densities, faster speeds and lower power usage with this vertical integration approach.”

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