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Soitec and CEA-Leti add 3D IC integration process customization for prototype demonstration

01 December 2009 | By Mark Osborne | News > Wafer Processing

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In an effort to reduce the learning cycles for customers attempting 3D IC integration, Soitec and long-term partner CEA-Leti plan to offer customized solutions for prototype work on both 200mm and 300mm wafers, which will include the necessary licensing.

“Leveraging Leti's 3D expertise and our well known bonding industrial experience, we can offer customers prototyping solutions as well as the processes they'll need for rapid ramp to full-scale production,” noted André-Jacques Auberton-Hervé, Soitec President and CEO.

This partnership will leverage CEA-Leti’s extensive work in this area, including our 3D integration technology toolbox,” said Laurent Malier, CEO of CEA-Leti. “Given CEA-Leti and Soitec’s successful history of innovation, industrialization and collaboration, we expect our global offer to significantly advance commercial adoption of 3D integration technologies.”

CEA-Leti offers 3D wafer-to-wafer technology and expertise. These include all the necessary process steps for different 3D approaches, such as connecting vias, and cost-effective technologies such as wafer pre-processing, bonding, thinning and TSV etching and filling, and post-processing wafer assembly. Soitec’s contribution to the partnership includes its ‘Smart Stacking’ technology, which enables wafer-to-wafer-level stacking of partially or fully processed circuits.


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