Online information source for semiconductor professionals
SOI process from Leti capable of 22nm low power devices
Popular articles
New Product: Applied Materials new EUV reticle etch system provides nanometer-level accuracy - 19 September 2011
Oberai discusses Magma’s move into solar PV yield management space - 29 August 2008
â??Velocityâ?? the new buzzword in Intelâ??s PQS annual awards - 12 April 2012
Applied Materials adds Jim Rogers to Board of Directors - 29 April 2008
New Product: ASML Brionâ??s Tachyon MB-SRAF enables OPC-like compute times - 19 September 2011
At the SOI Industry Consortium workshop being held in Leuven, Belgium,
French R&D organization, Leti said that its planer-SOI CMOS
technology met all the key requirements for implementation at the 22nm
node for low-power IC devices. Drain-induced barrier lowering (DIBL)
below 100mV/V has been demonstrated and SOI has been proven to enable
the reduction of electrostatic parasitics and that variability on
threshold voltage had been reduced by a factor of two compared with
FinFET technologies, at wafer and batch levels.
“Many transistor architectures have been proposed for the 22nm node and below. At Leti, we favored planar technologies for faster and easier transition to manufacturing,” said Laurent Malier, CEO of Leti. “Our recent results prove the strength of this approach. Together with the recent ARM results demonstrating power reduction on 45nm technology, we have proven that SOI technologies offer solutions for low power at a wide variety of nodes, including 22nm and below. Furthermore, we have demonstrated that planar SOI dramatically improves the energy performances of many products that will change our lives, while offering long-term success for many companies involved in these fast-growing markets.”
Leti also showed that fully depleted SOI (FDSOI) CMOS can be scaled down to the 10nm node through tuning the buried oxide and silicon layer thickness. FDSOI approach also addresses the variability issues at this node.