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SMIC yields on first HiPo 45nm wafer lots

30 June 2009 | By Mark Osborne | News > Wafer Processing

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With the help of its process partner IBM, SMIC has said it has produced device yields from test lots for its germanium strained high-performance 45nm process offering. SMIC has previously qualified IBM’s 45nm bulk CMOS low-power process.

"I'm delighted with the progress of SMIC's 45nm project team, which continues to meet rigorous deadlines, and we appreciate the excellent support from IBM throughout this progress," said Dr. Robert Tsu, SMIC's 45nm project leader and Associate Vice President of Logic Technology. "Integrating the silicon germanium process and achieving a well-yielded test chip from the very first yield lot is a significant technical accomplishment, and these accomplishments allow SMIC to provide a highly manufacturable technology to our customers."

"It verifies the IBM- licensed technology, validates our strategic decision to invest in advanced logic technologies, and enhances SMIC's position as the advanced logic technology leader in China,” commented Dr. Richard Chang, SMIC's President and CEO This 45nm GP process is a proven, robust, high yielding, and high performance technology that we anticipate can not only deliver better performance, reliability, and cost to our valued customers, but also help SMIC become even more competitive in China and worldwide."

SMIC also updated revenue guidance for its second quarter, noting that a rebound in customer orders was stronger than anticipated. Initially, SMIC has said that revenue would increase Q-on-Q by 58% to 62%, however, this would now be in the range of 76% to 78%.

However, the foundry remained cautious on believing this was a recovery, noting that it could just be an inventory replenishment phase due to the severe production order cutbacks the foundries had seen since the fourth quarter of 2008.

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