SMIC is to adopt Cadence Design Systems ‘Litho Physical Analyzer’ and ‘Litho Electrical Analyzer’ for IC designs entering into manufacturing for both the 65nm and 45nm nodes. Both tools enable better simulation of the impact of lithography processes on manufacturability of devices.
"The necessity to address physical and electrical variation at 65 and 45 nanometers requires a holistic approach that starts at the cell level and considers the entire context of the design," said Max Liu, VP of SMIC Design Services Center. "With the Cadence DFM flow, we could analyze cell and IP variability and accurately model their performance in real silicon. By characterizing and reducing the variability, our customers will be able to reduce guard-banding and to produce higher quality silicon. The solution also enables near-linear scalability, which is necessary for a full-chip electrical DFM verification flow."