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SilTerra offers 110nm half-node shrink

25 March 2009 | By Mark Osborne | News > Wafer Processing

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Malaysian foundry SilTerra is now offering a 10% linear optical shrink for its copper-based 130nm CMOS logic technology on 200mm wafers, claiming a 19% increase in die count compared to its 130nm process. Its ‘CL110G’ process incorporates eight layers of dual damascene copper metallization, borderless contacts and vias with FSG inter-metal dielectric. 

SilTerra said that the electrical device specification and SPICE model of CL110G are optimized to match with the original 130nm design. The foundry claimed that the cost-conscious offering was in demand, especially for customers to compete in the Indian and Chinese markets.

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