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Silterra demonstrates 130nm 8-Megabit SRAM

04 February 2005 | By Syanne Olson | News > Wafer Processing

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The Joint Development Project (JDP) between Silterra Malaysia Sdn. Bhd. and IMEC, has resulted in functional SRAM chips at Silterra's wafer fabrication facility in Malaysia. The device, an 8- megabit SRAM, was fabricated in the all-copper, foundry compatible 130nm CMOS process technology jointly developed by both companies.

"We are thrilled that the device works so well on the very first 0.13-micron wafer we ran in our fab," said Bruce Gray, president and interim CEO of Silterra. "The project is right on schedule with this demonstration of the phenomenal capabilities of both companies. We are now fine tuning the process, putting the customer design kit together, and we should be ready to start production in 2005 as planned."

A team of Silterra and IMEC engineers has worked diligently since the JDP was launched in July of this year. Two SRAM chips, an 8-megabit and a smaller 4-megabit device, were both functional on the initial development lot processed in Silterra's fab in Kulim, Malaysia. The process, based on IMEC's 0.13-micron technology platform, is major foundry compatible and supports up to eight layers of copper wiring.

Silterra plans to distribute the design kit to customers in Q2 2005 and start pilot production in July.

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