Online information source for semiconductor professionals

SEMATECH offers hope for 45nm low-k target

28 September 2005 | By Syanne Olson | News > Wafer Processing

Popular articles

Oberai discusses Magma’s move into solar PV yield management space - 29 August 2008

New Product: Applied Materials new EUV reticle etch system provides nanometer-level accuracy - 19 September 2011

‚??Velocity‚?? the new buzzword in Intel‚??s PQS annual awards - 12 April 2012

Applied Materials adds Jim Rogers to Board of Directors - 29 April 2008

TSMC honors suppliers at annual Supply Chain Management Forum - 03 December 2008

In a paper presented at the Advanced Metalization Conference (AMC) at Colorado Springs, CO, SEMATECH and Rohm and Haas Electronic Materials researchers revealed work being carried out to provide a k-effective (keff) value of 2.5 in dual damascene work flows targeted by the ITRS roadmap for the 45nm node.

"The dual damascene integration that our team developed offers a potential solution for blocking precursor penetration and minimizing process-induced damage typically observed with ULK dielectrics containing interconnected pores," said Ward Engbrecht, lead author and a SEMATECH copper low-k integration project engineer.

The SEMATECH approach deposits the dielectric films by spin-on-deposition to form a matrix-porogen system that can be integrated as a dense material through chemical mechanical planarization, Rohm and Haas "Solid First" ILD process. The porogen then can be removed in a thermally-assisted ultraviolet cure process to create a system with a keff value of approximately 2.5. The Rohm and Haas spin-on low-k material is based on nanometer size pore forming polymers in the methylsilsesquioxane family, which the company patented in 2001.

"Our results show a process that has real promise as a solution for k-effective at 45 nm," said Sitaram Arkalgud, SEMATECH's interconnect director. "We will continue to refine our approach with an eye to reliability and eventual high-volume manufacturing."

Related articles

SEMATECH prepares 3D-IC workshop on manufacturing and reliability - 21 August 2008

Litho metrology challenges for the 45nm technology node and beyond - 01 March 2006

EVENT: SEMATECH Hosting Advanced Gate Stack Symposium - 15 September 2005

UMC establishes 22nm node R&D partnership with SEMATECH - 28 July 2008

Grand challenges of advanced resist technology - 01 June 2005

Reader comments

No comments yet!

Post your comment

Name:
Email:
Please enter the word you see in the image below: