Sematech’s CNSE-based 3D Interconnect program has yielded some encouraging results that will likely improve on current 3D interconnect technologies. Research has shown that a series of tool and process hardening improvements has advanced wafer-to-wafer bonding alignment accuracies at the company’s UAlbany campus, while further advances have been made in 3D metrology and failure analysis techniques to complement bonding tool development.
The results of this research were presented at the 2010 IEEE International Interconnect Technology Conference (IITC) on June 9th. As key enabling process steps for 3D interconnection of wafer stacking - and, potentially, volume production of TSVs, these findings and advancements will aid in meeting the growing demand for smaller, lower-power chips.
“Through collaborative research, our goal is to develop and characterize new approaches to implementing 3D,” said Sitaram Arkalgud, director of Sematech’s 3D Interconnect Program. “These leading-edge results, which have a direct impact on processing costs, demonstrate SEMATECH’s leadership and innovative techniques that pave the way for low-cost 3D IC integration.”