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SEMATECH details presence at SEMICON West

24 June 2011 | By Mark Osborne | News > Wafer Processing

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SEMATECH and International SEMATECH Manufacturing Initiative (ISMI) have highlighted the numerous presentations and public workshops the R&D organisation will be conducting during the annual SEMICON West event in San Francisco from July 11–15.

“Both SEMATECH and ISMI recognize that the industry needs innovative and practical solutions for continued scaling of semiconductor technologies that can easily be incorporated into real-world manufacturing environments,” said Dan Armbrust, president and CEO, SEMATECH. “This year’s SEMICON West will be an important forum for our industry to come together and find best ways to address complex technology challenges. We look forward to sharing our technical knowledge and best practices to help drive our industry forward.”

Raj Jammy, SEMATECH’s vice president of Emerging Technologies, “Heterogeneous Integration of High Mobility Ge/III-V Channels on Si,” July 12 at 11 a.m.

David Gilmer, SEMATECH’s project engineer of Advanced Memory Technologies, “Metal-Oxide based RRAM Materials and Development,” July 12 at 11:30 a.m.

Stefan Wurm, SEMATECH’s associate director of Lithography, “EUV Mask Infrastructure (EMI) Partnership,” July 13 at 11:05 a.m.

Sitaram Arkalgud, SEMATECH’s director of Interconnect, will co-moderate panel session 1 in the 3D in the Deep Submicron Era, July 13 at 1:50 p.m.

Chris Hobbs, SEMATECH’s CMOS scaling program manager of Front End Process, “Non-Planar CMOS Device Challenges and Opportunities,” July 14 at the NCCAVS Advanced Process and Integration in Semiconductor Technologies session.

Additionally, SEMATECH and ISMI experts will host and present at various public workshops, at the Marriott Marquis, during SEMICON West:

Equipment suppliers will identify opportunities and bridge understandings on enabling 3D technology in the wafer handling process space at the workshop Enabling 3D: Temporary Bonding Workshop on July 11 at 1 p.m.

Equipment suppliers and end users will meet to address topics such as SEMI S23 reporting and goals, applying high temperature process cooling water on process tools, and idle mode interface for process equipment subsystems at the ISMI Equipment Energy Workshop on July 12 at 8 a.m.

Equipment suppliers will share their plans on how new and existing wafer metrology technologies can be used, modified, or enhanced to measure and improve 3D interconnect processes at SEMATECH's 3D Metrology Workshop on July 13 at 12:00 p.m.

Co-sponsored by SEMI and ISMI, the EDA Workshop will focus on the equipment data acquisition (EDA) interface requirements and implementation for the 0710 standards freeze level. Participants will be able to discuss with industry experts how the changes for the new freeze level can be implemented and evaluated on July 13 at 1 p.m.

A day-long preview of this year’s International Technology Roadmap for Semiconductors will be offered at the Summer ITRS Public Conference on July 13.

Hosted by SEMATECH, in collaboration with Fraunhofer IZFP, the fifth workshop on Stress Management for 3D ICs using Through Silicon Vias will discuss product-level reliability, including product qualification, product level test requirements, and failure analysis on July 14 at 9 a.m.

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