Online information source for semiconductor professionals

Semiconductor Leading Edge Technologies Inc, (SELETE) the Japanese led IC manufacturers consortium has concluded process development work on "hp 65nm" node CMOS process modules.

SELETE is claiming a key breakthrough whereby transistors employ a hafnium-silicate as the gate dielectric that complies with the low standby power ratings as stated are required within the latest ITRS roadmap.

Also qualified is a two-level metal interconnect which employs an "effective" low-k of 2.7 with a Young's modulus of 10Gpa, which is consistent with first generation low-k materials that had an effective k of 3.0-3.2, while achieving a similar 10Gpa.

Uniformity across 300mm wafers was excellent and reliability factors TDDB (Time Dependent Dielectric Breakdown) on the transistors were deemed sufficient for initial volume production.