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Panasonic and Renesas use HKMG with ultra-low-k for 32nm SoC devices

09 October 2008 | By Mark Osborne | News > Wafer Processing

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Panasonic and Renesas Technology Long-standing technology partners Panasonic and Renesas Technology have said they expect to use metal gates and high-k dielectrics for the gate structure with a new ultra low-k dielectric for the interconnect on 32nm SoC devices for future mobile and digital home appliance products.

To achieve a device using complementary metal-insulator semiconductor (CMIS) technology, a type of complementary Metal Oxide Semiconductor (CMOS), at a 32nm node, an ultra-thin film cap layer is applied at the atomic level to transistors with a metal/high-k gate stack structure under optimized conditions. This enables development of a conventional transistor configuration, which allows the use of an oxidized silicon film as the gate insulation layer.

The introduction of the cap layer has, according to the companies, been shown to improve transistor reliability in practical use and suppress distribution of electrical characteristics between transistors, thereby enabling the operation of large-scale circuits.

The aim is to produce high-speed signal processing with very low power consumption. Renesas was one of the earliest chip manufacturers to launch 45nm chips; however they did not adopt HKMG technologies at that node.



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