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Oki Electric reveals fully depleted SOI process with reverse polarity

06 October 2005 | By Syanne Olson | News > Wafer Processing

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Oki Electric Industry Co., Ltd has presented details of its fully depleted SOI process that it claims reduces standby leakage current by over 90 percent yet retains performance figures of its previous SOI devices. This was achieved by using a transistor that had a non-doped body and non-overlap type SOI structure. The device was revealed during 2005 SOI Conference in Honolulu, Hawaii.

"With growth in the use of personal and mobile communication products, demands for lower power consumption LSIs have also been increasing. To respond to such needs we have been researching and developing the fully depleted SOI technology, which enables a high performance, low power consumption LSI," said Akira Kamo, President of Silicon Solutions Company at Oki Electric. "We are excited at this experimental stage achievement. Confirming high-speed performance while significantly reducing off-leakage current enables us to accelerate development in sensor network products using coin batteries and solar power going forward."

The experimental process and design uses P+ gate for NMOS, N+gate for PMOS, the opposite in polarity of normal CMOS gates. This enables better compatibility with conventional processes by using a low-cost polysilicon gate process, while also achieving a low-cost structure. The breakthrough overcomes the inherent problems of parasitic capacitance in SOI devices by using a non-overlap source/drain structure, according to the company. The non-overlap type structure transistor has been seen in bulk device used in high-speed, high-performance applications, but the Oki development is the first to use SOI for super low off-leak applications, the company claims.

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