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Novellus joins IBM and CNSE on resist strip process development

11 February 2010 | By Mark Osborne | News > Wafer Processing

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A new technology development collaboration has been established between Novellus Systems, IBM and the College of Nanoscale Science and Engineering (CNSE) at CNSE’s Albany NanoTech Complex to develop advanced, residue-free photoresist strip technologies for leading-edge processes for the 28nm and 22nm nodes.

A range of photoresist removal processes, including high-dose implant strip (HDIS) processes that are compatible with high-k metal gate technology, and damage-free etch strip chemistry used for ultra-low-k dielectric structures are said to be the first priority of the collaboration.

“IBM is committed to working with Novellus Systems and the College of Nanoscale Science and Engineering in this newly-established technology collaboration, where our initial focus is on optimizing these advanced photoresist strip technologies for our industry-leading high-k metal gate transistor structures,” said Paul Farrar, Vice President of Process Development, IBM. “Close collaboration with equipment suppliers through the consortium of world-class companies at CNSE’s Albany NanoTech is critical to bringing leading-edge technology to market for the benefit of IBM and its alliance partners.”

The work is also being undertaken for the benefit of the IBM’s technology alliance partners.

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