Online information source for semiconductor professionals

New Product: Invarium offers ‚??wet‚?? versus ‚??dry‚?? lithography patterning synthesis trade-offs:

18 September 2006 | By Mark Osborne | News > Lithography

Popular articles

New Product: Applied Materials new EUV reticle etch system provides nanometer-level accuracy - 19 September 2011

Oberai discusses Magma’s move into solar PV yield management space - 29 August 2008

‚??Velocity‚?? the new buzzword in Intel‚??s PQS annual awards - 12 April 2012

Applied Materials adds Jim Rogers to Board of Directors - 29 April 2008

TSMC honors suppliers at annual Supply Chain Management Forum - 03 December 2008

InvariumProduct Briefing Outline: Invarium has launched ‘Dimension45/32' design to manufacturing synthesis tools to specifically address patterning challenges at the 45 and 32nm nodes. Dimension45/32 is designed to enable lithography and photomask synthesis teams to select and optimize the right combination of exposure strategies and full-chip photomask layout synthesis.  It also enables layout retargeting, if necessary, to achieve the best post-etch results on silicon, with, according to the company, the largest process window and best yield. Dimension45/32 is currently being customer-qualified in North America, and the company has stated that a second customer qualification program will immediately commence in Asia.

Problem: Extremely low k1 (sub 0.3), even with immersion, requires the best possible CD control for robust manufacturability. Slack has to be picked up by patterning synthesis software that takes into consideration manufacturing inaccuracies such as overlay, post-etch CD uniformity and dose and focus variability. At the 45nm node, immersion lithography is generally considered necessary for front-end layers such as diffusion, gate poly and contact. But the approach to be taken for metal routing layers M2 to M6 or beyond is less obvious. Cost considerations as well as the availability of a sufficient number of immersion tools make an all-immersion solution at 45 nm questionable and expensive. Another key consideration is developing RET/OPC compensation solutions for low k1 realms that can be both expensive and time consuming as part of the design flow time to market window.

Solution: Dimension45/32 is based on Invarium's target-point methodology that adds critical production information to the design flow stages in a layered approach that considers the key manufacturability issues of a design at both critical and non-critical layers. Etch, Litho, and Mask processes all have different characteristics that degrade the pattern in different ways. For instance, the offset between the litho and etch contours may not be constant from one location to another. Therefore, an etch correction based on simple rule-based biases is insufficient. Invarium believes it is inadequate to model all these effects in a single lumped model. For optimum accuracy, it is necessary to understand each process effect by itself, and then to sequentially invert the process effects in the reverse order of the patterning process. Dimension45/32 thus provides a ‘correct-by-construction' methodology. When this is achieved the process window is improved and reduces lengthy RET/OPC rendering and mask costs as well as enabling critical decisions to be made. These decisions include deciding which type of lithography technology can be safely used in volume production environments that meet or exceed yield targets for both dry and wet lithography tool choice.  

Applications: Critical layers; Gate Poly, Active, Contact, and Metal 1-2. Less critical; Metal routing layers M2 through M6 or M7.

Platform: Based on Invarium's ‘DimensionPPC' platform, Dimension45/32 is a DRC-clean GDS-II layout, and the output is a GDS-II or Oasis layout ready for mask data preparation (MDP).

Availability: September 2006 onwards.

Related articles

New Product: Invarium reveals ‚??Process and Proximity Compensation‚?Ě software for 65nm layout-to-m - 09 February 2006

Balancing Power and Fuel Usage of PFC Abatement Options for Minimisation of Etch Tool Global Warming - 01 December 2002

New Product: Synopsys Proteus LRC offers 28nm and below lithography verification - 02 March 2011

CEA-Leti research achieves CMOS compatibility with synthetic silicon nanowires - 07 October 2009

New Product: Molecular Imprints‚?? ‚??Imprio‚?? 300 assists 32nm lithography R&D - 25 February 2008

Reader comments

No comments yet!

Post your comment

Please enter the word you see in the image below: