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Material limits effect low-k

05 February 2005 | By Syanne Olson | News > Wafer Processing

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Presenters at the SEMATECH Low-k Symposium, which attracted approximately 140 technologists to San Diego in late October, appeared to sustain SEMATECH's position that interconnect materials below 2.5 k-effective may be too expensive to develop and too difficult to work with to be economically practical for all design schemes. The search for low-k materials to improve semiconductor interconnects may have reached certain practical limits. Future work will focus less on new, ultra low-k materials, and more on enhancing improvements in process and design, conference participants indicated.

"For several years now, the emphasis among suppliers and in the industry has been to drive relentlessly toward lower and lower k-values," said Klaus Pfeifer, Interconnect Program Manager at SEMATECH. "But that approach has its drawbacks, because at the 45nm node, ultra low-k dielectrics are so fragile and sustain so much damage from standard processing that the issues associated with incorporating them can essentially negate the advantages provided by these ultra low-k materials."

And while it may be technically possible to solve these processing issues, and even to drive interconnect materials below 2.5 k-effective, doing so is not likely to be economical, according to Andreas Knorr, SEMATECH Program Manager and a conference organizer.

"Based on simulation data presented at the symposium, the dominant factor is transistor performance, especially for devices with short signal lengths between transistors," Knorr noted. "So even if you improve your k-effective within such devices, you have almost no increase in performance. And if you look at interconnectdominated circuits that have long signal lines, the simulations show that you might get a five percent performance increase for a 10 percent reduction in k-effective. But from a dollars-and-cents perspective, that result might not be worthwhile."

Instead, Pfeifer and Knorr say engineers are heading toward an alternative strategy that focuses on refining interconnect process technologies - notably etch, ash and cleans - and concentrates on improving circuit design methodologies.

"In this approach, the designers would use the most advanced and expensive processes only at levels and circuits that are limited by capacitance or RC product performance, and would use conventional, more robust processes and materials for all other levels and circuits," said Knorr.

Longer term, cost-effective interconnect efforts are likely to focus on 3D technology and heterogeneous integration, according to Ken Monnig, SEMATECH's Associate Director of Interconnect. 3D technology involves stacking ICs physically and connecting them through vias on the chips themselves. Heterogeneous integration enhances established process schemes by allowing them to be integrated with advanced ones at selected places within an integrated device .

During 2005, SEMATECH plans to sponsor two public workshops in 3D technology and develop cost models for 3D architectures, noted Sitaram Arkalgud, Interconnect Director. "We view this as an important initiative for our member companies and the industry," Arkalgud said.

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