Online information source for semiconductor professionals

Macronix reveals 8-layer, 75nm half-pitch, 3D VG (Vertical Gate) NAND flash device

17 June 2010 | By Mark Osborne | News > Wafer Processing

Popular articles

Oberai discusses Magma’s move into solar PV yield management space - 29 August 2008

‚??Velocity‚?? the new buzzword in Intel‚??s PQS annual awards - 12 April 2012

Applied Materials adds Jim Rogers to Board of Directors - 29 April 2008

TSMC honors suppliers at annual Supply Chain Management Forum - 03 December 2008

Sematech Litho Forum: Sematech mulling multi-beam mask writer effort - 12 May 2010

As one of the 8 highlight papers selected for the 2010 Symposium on VLSI Technology, Macronix International is presenting a paper demonstrating the fabrication of an 8-layer, 75nm half-pitch, 3D VG (Vertical Gate) NAND Flash using a junction-free BE-SONOS device. Macronix claims this technology provides a successful path to the most scalable and most efficient 3D NAND Flash using its patented BE- SONOS (barrier engineering) charge-trapping technology and 3D decoding architecture.

"Traditional NAND Flash will be facing technology barrier when it scales to below 2Xnm node," said C. Y. Lu, President of Macronix. "The three-dimensional memory cell array structure has been proposed to be the most promising candidate for NAND Flash to shrink to below 1Xnm. Macronix's 3D memory research results based on our own BE-SONOS technology have set a new milestone for next generation NAND Flash to meet high density capacity requirement."

Several 3D NAND Flash structures have been proposed, such as P-BiCS (Pipe-shaped Bit Cost Scalable), TCAT (Terabit Cell Array Transistor), VSAT (Vertical Stacked Array Transistor) and VG (Vertical Gate). However, according to Macronix, in a 3D structure interference (cross talk) occurs not only between neighbouring cells in the same plane but also between vertical neighbours in adjacent planes. This has become a new challenge in addition to the conventional Moore's law scaling issues.

Through detailed analyses on scalability, reading current (which determines read speed performance) and cross talk, Macronix's work has chosen the VG architecture, believing it is the best approach. Simulation work showed this structure could be scaled to 25nm node in a 3D array, providing density far beyond conventional 2D NAND Flash.

Related articles

Hynix delays 300mm fab ramp - 01 April 2008

ECD Seed Layer for Inlaid Copper Metallisation - 01 June 2000

IMFT migrates to 34nm NAND flash production - 24 November 2008

NAND flash capex to fall nearly 60%, says DRAMeXchange - 17 February 2009

FSI International extends ‚??ViPR‚?? technology to NAND flash production - 24 March 2009

Reader comments

No comments yet!

Post your comment

Name:
Email:
Please enter the word you see in the image below: