ASML is now engaged in “full integration” of the NXE: 3100 EUV scanner expected to begin shipping in the second half of this year, ASML product marketing director Rard de Leeuw said at the Sematech Litho Forum in New York City. Six of the EUV systems, capable of 60 wph throughputs, will be shipped in the second half of this year, kicking off process development activities in preparation for high-volume manufacturing. ASML’s roadmap calls for the high-volume NXT:3300B EUV scanner to begin shipping in the second quarter of 2012.
“The source is now at ASML and is under installation, and five sets of optics have been made by Zeiss with flare now down to 4%. It looks good,” de Leeuw said.
Device makers at the Sematech meeting said they expect to begin using EUV for critical layers in the 2015-2016 time frame.
Bryan Rice, lithography program manager at Sematech’s Albany, N.Y. center, said much of the industry’s anxiety about EUV now centers on its cost effectiveness. “It is difficult to do a cost comparison when the technology is not yet at the required level of maturity. When it is, EUV will be a cost winner,” said Rice, an Intel assignee to Sematech.
Rice cited the improvement in the ability to pump air out of the exposure chamber as one example of EUV’s progress. “Do you know how long it used to take to achieve vacuum? It took nearly a week. Now, ASML can do that in 40 minutes. To me, that rate of progress is very impressive.” De Leeuw said the NXE:3100 remains too large, measuring 10 m long and 3 m wide. “We need to act here, to reduce the footprint” when the high-volume 3300 series scanners begin shipping. “We expect a 40% reduction, to 50 square meters of footprint, with the subfab not larger than the tool.”
ASML is talking to customers now about the NXT:3300 and expects to take its first purchase orders in July. The NXT:3300 will have improved Zeiss optics with a 0.32 NA, and a throughput of 125 wph, largely due to a sharp increase in the source power to 250 W.
EUV can be extended by reducing the 13.4 nm wavelength to 6.8 nm, now an active area of research. “We are studying how to extend EUV, with high NA optics and by cutting the wavelength in half,” de Leeuw said.
Toshikazu Umatate, a vice president at Nikon Precision, said Nikon’s high-volume EUV scanner will be ready in 2014-2015. “We want to match the 16 nm node timing,” Umatate said, adding that Nikon is “coordinating investments with the infrastructure developers.”
Nikon is monitoring the consolidation in the industry, and its likely impact on scanner manufacturers. The five-largest chip companies now spend about 50% of the total industry’s capital investments. While lithography vendors sold roughly a thousand tools in 2000, a decade later the expectation is for shipments of only 200 leading-edge exposure tools in 2010. “It is a higher risk, all-or-nothing situation now,” he said.
De Leeuw also dwelled on ASML’s rising R&D expenditures, saying EUV has cost the Dutch companies $1.5B thus far, with Zeiss spending another $600M. “EUV is here to stay, for many, many years,” he said. However, ASML projects that the semiconductor industry will consume an estimated 167 EUV tools overall. To recoup its investments, the ASML manager said $10B in EUV revenues is needed.
Others also are worried how to recoup their costs. With the track added, an EUV cluster will exceed $100M, said Julie Planchet, a manager at Dow Chemical Co. That unpalatable price tag will require a “new business model” for infrastructure suppliers who will not be able to afford an EUV tool of their own for development purposes.
On the plus side, several speakers at the Litho Forum said the widespread proliferation of mobile and consumer electronics will push semiconductor revenues up, making EUV affordable. Garry Patton, vice president of IBM’s Semiconductor Research and Development Center in East Fishkill, N.Y., said semiconductor revenues were only $1B in 1962, and are now pushing $300B. In the last decade alone, ICs for consumer electronics systems have increased 10X in value. That growth has helped justify the sharp increase in R&D spending, which Patton said has increased 10X in the last decade.
“EUV is the next frontier. Double patterning is too expensive, and by 2015-2016, at the 11 nm node, we will certainly need EUV,” Patton said. Meanwhile, the industry will employ source-mask optimization (SMO) and double patterning, along with design restrictions to ensure litho-friendly patterns. With EUV, Patton said, we can relax some of the constraints on the mask and the light source and avoid the need for double patterning and design restrictions.
“EUV is so important, we need to move full speed ahead,” Patton said, adding that it will be “quite challenging to make it happen by 2015-2016.” Even though immersion lithography was a relatively straightforward addition of water, it took five years for the chip industry to go from the early concept stage to full production in 2008 with “wet” 193 nm scanners. With EUV, there are at least six major changes, including the use of reflective optics and the new wavelength. “There is no pellicle for the EUV masks, and the ability to inspect the mask is one of the key challenges. Getting the source to the right kind of level, and resists, are among the other main challenges,” Patton said.
Sematech CEO Dan Armbrust said rapid progress is needed to reduce the number of defects on the EUV mask blanks, an issue cited by the Litho Forum survey as one of the two key challenges facing EUV lithography (source power was given nearly equal weight in the survey). Sematech is asking the two EUV mask blank suppliers to achieve a 10X reduction in defects, starting with a 2X reduction by July and a further 5X reduction thereafter.
“Two more orders (of defect reduction) are necessary at the supplier locations. If the mask blank defect issue is not solved, all the rest of our efforts will be for naught,” Armbrust said.
Sematech has organized the EUV Mask Inspection (EMI) program for mask blank and patterned mask inspection tools, with seven founding partners committing to a total of $200-300M in funding for the three inspection tools required. Geert Vandenberghe, an IMEC program manager who was called upon to stand in at the Litho Forum for IMEC CEO Luc Van den hove when the volcanic ash forced cancellation of Van den hove’s flight from Belgium to New York, said IMEC has processed a cumulative total of 2,000 wafers on its EUV Advanced Development Tool (ADT) from ASML since June 2008.
“We are on a path toward use of EUV at the 16 nm node, but the No. 1 critical issue has been mask inspection,” Vandenberghe said. He detailed IMEC’s work on EUV resist development, noting that sulfur-containing outgassing remains a concern.
Several device makers took the stage at the Forum, saying they need EUV to relieve the cost pressures presented by double patterning. Jeong-Ho Yeo, a Samsung process development manager, said Samsung “needs to insert double patterning for the 40 nm half-pitch. We hope to go to EUV for 20 nm half-pitch. We want to reduce our costs in three ways: by design rule shrinks, increasing the wafer size, and increasing the throughput of the scanners.”
With double patterning estimated to be 2-3X more expensive than single patterning, Samsung seeks to “either reduce the cost of double patterning or shift to EUV. Low-cost double patterning and high-throughput EUV are crucial in order to stay on the memory roadmap,” Yeo said.
Obert Wood, a GlobalFoundries staff member who heads up the EUV development program at the Fishkill Alliance, said 193 nm immersion lithography begins to run out of steam at the 40 nm half pitch. Showing images of contact layers made with both EUV and immersion scanners, Wood said EUV “can resolve spaces of 20 nm between the contact holes with perfect alignment.”
However, Wood cautioned that with Nikon planning to introduce its 0.4 NA high-volume EUV scanner in 2014, “it is slightly alarming that there will be only one supplier for the next few years.” Also, Wood said “mask blank defects are an order of magnitude higher that what is needed for pilot production.”
Turning to the resist development challenge, Wood said line edge roughness (LER) is now 2.5 nm, while “the spec calls for 1.5 nm. We have one resist which currently works for sub-20 nm resolution, but the line width roughness (LWR) is still higher than it needs to be. Pattern collapse is an issue with these thin resists.”
Wood said the “early news is that the quality of the EUV optics from Zeiss is better than expected. Zeiss has done a lot of work on high-refectivity optics, and there is no fundamental reason why we cannot upgrade eventually to 0.7 NA.”
Wood, who played a key role in the early EUV development at Bell Labs in the 1970s and 80s, said device manufacturers are concerned about cost of ownership (CoO) issues. The source power must increase in order to hit the throughput targets outlined by ASML. “Throughput is so important. Unless throughput is more than 100 wph, EUV does not show much cost advantage. My guess is that the early beta tools will not meet the 60 wafers per hour target if the source power goals are not met. And the blank costs are very much an unknown.”
Noting that EUV is clearly too late for the 22 nm node, Wood added that for some chip manufacturers EUV may also miss the 15 nm node. “I think it would be unwise to depend on EUV for the 15 nm generation, though there is some chance the infrastructure will be sufficiently ready in 2013 for early work at that node.”