The Sematech Litho Forum, held in New York City, concluded with the meeting’s traditional survey, with respondents this year indicating guarded confidence that EUV lithography will be a workhorse solution by 2014 for critical layers. The 131 respondents were asked what type of exposure technology would be employed for the gate and contact layers. In 2012, 60% said double patterning (DP) with 193 nm scanners would pattern those critical layers, largely for 22 nm technology generation devices.
By 2014-15, when leading edge companies are beginning to make 16 nm products, 43.8% said EUV would be used for the gate, and 36% said EUV would be needed for contacts. Double patterning had fallen into second place, with about 36% of the survey respondents endorsing DP in the 2014-15 time frame for critical layers.
By 2016-18, when leading-edge chip makers are at the 11 nm node, 38% said EUV would be used, while another 22.6% voted for “extended EUV” with higher NA optics. By 2016-18, double patterning will have dropped to 14%, the respondents said.
The Litho Forum survey showed deep concerns about lithography costs. For EUV, mask defects and source power and source lifetime were rated as major concerns, along with cost of ownership. For double patterning, cost of ownership was the top-rated issue, followed by alignment and overlay control.
Bryan Rice, director of the Sematech lithography program, said “EUV is now considered the dominant resource going forward, with double patterning seen as what we have to do out of necessity until EUV is ready.” The support for EUV stems from perceptions that it is an extendible solution “capable of doing single-exposure patterning down to the 8 nm node.”
Asked which lithography techniques deserve continued support, EUV received the top ranking by 52% of the respondents, but a respectable 46% said direct-write e-beam lithography should receive further attention. A smaller number said self-assembling patterning techniques have shown enough promise to merit financial support.
John Warlaumont, Sematech’s senior manager at the Albany site and vice president of advanced technology, said previous Litho Forums were marked by spirited debates about whether EUV, e-beam, 157 nm, or other forms of lithography would emerge supreme. “This year, there is less discussion about whether solution A or solution B will win out. The question now is how to make EUV a success,” he said.
Obert Wood, a GlobalFoundries manager who runs the EUV program for the Fishkill Alliance, gave a detailed presentation about the progress and challenges with EUV lithography. Significant progress needs to be made in both mask blank defects, which are an order of magnitude too high now, and source power. About 400 Watts of clean EUV source power will be needed for high-volume manufacturing tools, beginning with the NXE 3300 series from ASML in 2012.
“EUV clearly will be too late for the 22 nm logic node, or the 40 nm half pitch,” Wood said. “By 2013, it may be ready for the early adopters of the 15 nm logic or possibly the equivalent memory node. Where EUV will see wider adoption will be for the 11 nm logic node in 2017,” Wood said.