Online information source for semiconductor professionals

IMEC reduces high-k/metal gate process steps from 15 to 9

17 June 2008 | By Mark Osborne | News > Wafer Processing

Popular articles

New Product: Applied Materials new EUV reticle etch system provides nanometer-level accuracy - 19 September 2011

Oberai discusses Magma’s move into solar PV yield management space - 29 August 2008

‚??Velocity‚?? the new buzzword in Intel‚??s PQS annual awards - 12 April 2012

Applied Materials adds Jim Rogers to Board of Directors - 29 April 2008

New Product: ASML Brion‚??s Tachyon MB-SRAF enables OPC-like compute times - 19 September 2011

IMECIMEC has revealed at the VLSI Symposium that its collaboration partners on its sub-32nm CMOS program have developed a simplified high-k/metal gate process that reduces the number of process steps from 15 to 9. The research center also demonstrated improvements to inverter delay from 15p/s to 10p/s.

By applying conventional stress boosters to its gate-first dual-metal dual-dielectric high-k/metal gate CMOS, IMEC said that its researchers had increased the performance of nMOS and pMOS transistors by 16 percent and 11 percent respectively. For the first time, the compatibility of conventional stress memorization techniques with high-k/metal gate has been demonstrated, IMEC noted.

IMEC’s simplified high-k/metal gate process uses a single-metal dual-dielectric approach, using soft-mask processes and wet removal chemistry, compared to existing dual-metal dual-dielectric schemes. According to IMEC the simplified approach reduces the complexity by 40 percent or 6 process steps compared to dual-metal dual-dielectric. Another benefit is that the new approach allows for a simpler gate-etch profile control that will be easier to scale, IMEC said.

Both gate-first and gate-last integration schemes are now manufacturable with the gate-first approach seen as a low-cost option with better integration into standard CMOS process flows. The gate-first approach when using a dual-metal dual-dielectric process flow can be successful when using hard masks to pattern nMOS and pMOS regions selectively.

IMEC also noted that a ‘high-performance’ (low-Vt) high-k/metal-gate CMOS had been developed, which used a thin dielectric cap between the gate dielectric and metal gate.

Related articles

CMOS integration results for the 90nm technology node - 01 March 2003

ASM offers single metal gate stack for 32nm logic processes - 19 May 2008

UMC looks at hybrid gate-first and gate-last techniques - 10 December 2009

The integration of high-k dielectrics: A story of modest achievements - 01 September 2002

TSMC touts gate-last HKMG for 28nm low-power applications - 24 August 2009

Reader comments

No comments yet!

Post your comment

Please enter the word you see in the image below: