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IMEC reduces high-k/metal gate process steps from 15 to 9

17 June 2008 | By Mark Osborne | News > Wafer Processing

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IMECIMEC has revealed at the VLSI Symposium that its collaboration partners on its sub-32nm CMOS program have developed a simplified high-k/metal gate process that reduces the number of process steps from 15 to 9. The research center also demonstrated improvements to inverter delay from 15p/s to 10p/s.

By applying conventional stress boosters to its gate-first dual-metal dual-dielectric high-k/metal gate CMOS, IMEC said that its researchers had increased the performance of nMOS and pMOS transistors by 16 percent and 11 percent respectively. For the first time, the compatibility of conventional stress memorization techniques with high-k/metal gate has been demonstrated, IMEC noted.

IMEC’s simplified high-k/metal gate process uses a single-metal dual-dielectric approach, using soft-mask processes and wet removal chemistry, compared to existing dual-metal dual-dielectric schemes. According to IMEC the simplified approach reduces the complexity by 40 percent or 6 process steps compared to dual-metal dual-dielectric. Another benefit is that the new approach allows for a simpler gate-etch profile control that will be easier to scale, IMEC said.

Both gate-first and gate-last integration schemes are now manufacturable with the gate-first approach seen as a low-cost option with better integration into standard CMOS process flows. The gate-first approach when using a dual-metal dual-dielectric process flow can be successful when using hard masks to pattern nMOS and pMOS regions selectively.

IMEC also noted that a ‘high-performance’ (low-Vt) high-k/metal-gate CMOS had been developed, which used a thin dielectric cap between the gate dielectric and metal gate.

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