Online information source for semiconductor professionals

IMEC prepares industry for introduction of vertical transistors

14 June 2010 | By Dave Lammers | News >

Popular articles

Oberai discusses Magma’s move into solar PV yield management space - 29 August 2008

‚??Velocity‚?? the new buzzword in Intel‚??s PQS annual awards - 12 April 2012

Applied Materials adds Jim Rogers to Board of Directors - 29 April 2008

TSMC honors suppliers at annual Supply Chain Management Forum - 03 December 2008

Sematech Litho Forum: Sematech mulling multi-beam mask writer effort - 12 May 2010

According to industry sources attending the IMEC Technology Forum in Leuven, Belgium, the chip industry is currently preparing for the introduction of vertical transistors. Shang-yi Chiang, senior vice president of research and development at TSMC said that the company has already decided to use a vertical transistor structure at the 14nm node.

"We looked at the basic device physics, and came to a decision that we cannot use a planar structure at the 14nm node. With a vertical transistor we have better control of the channel," said Chiang. TSMC will move from 28nm to 20nm, and then to the 14nm generation by the middle of this decade.

IMEC has also now opened the additional 1,200m2 of its cleanroom, which adds 50% to the facility that was opened five years ago. The added space was included to accommodate the NXT: 3100 EUV tool expected to be installed at IMEC by the end of 2010.

IMEC's Thomas Hoffmann, director of the Front End of the Line (FEOL) program, said, "Today we are getting a lot of questions about FinFETs from the fabless companies that participate in our Insite program." TSMC's plans, as well as persistent rumors that Intel may adopt vertical transistors at the 22nm node, are driving the preparation efforts, he added.

"One challenge we and our partners have is unraveling how a gate-last technology on FinFETs will work. For companies moving to FinFETs at either the 22 or 16nm nodes, they want to know what the implications for high-k/metal gate if they go to a non-planar structure," Hoffmann said in an interview at the IMEC facilities in Leuven.

The gate-last approach, first adopted by Intel at the 45nm node and also selected by foundry TSMC for its 28nm high-k process, has several advantages, Hoffmann said. The PMOS threshold voltage appears to be more stable with the gate-last approach, and an additional strain is achieved on the silicon channel in the PMOS transistor when the polysilicon replacement is removed. However, the gate-first camp, which includes GlobalFoundries, IBM, and the other members of the Fishkill Alliance, argue that the gate-first approach delivers a smaller die size than the gate last approach. Several companies which rely on foundries are now conducting shuttle runs to compare the performance and area of the competing approaches to high-k deposition.

"For low-power logic at 28nm, the gate-first approach can definitely meet the technology targets," Hoffmann said.

IMEC's extra cleanroom space

Related articles

Metal-gate integration challenges - 01 March 2005

Future DRAM on logic 3D IC revealed by IMEC - 01 October 2009

IMEC reduces high-k/metal gate process steps from 15 to 9 - 17 June 2008

Meeting the doping challenges: the case for plasma doping - 01 March 2008

SOI Industry Consortium attracts IMEC - 26 February 2009

Reader comments

No comments yet!

Post your comment

Please enter the word you see in the image below: