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IMEC demonstrates fully functional 3D stacked ICs

14 October 2008 | By Mark Osborne | News > Wafer Processing

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IMEC: Test-chip taped for assessing design rules and models for 3D-SIC technology.IMECs research into 3D-SIC (3D stacked IC) technology has reached a new milestone with the announcement that it has recently demonstrated the first functional 3D integrated circuits obtained by die-to-die stacking using 5µm Cu through-silicon vias (TSV). The work was carried out on 200mm wafers using its 130nm CMOS process with the inclusion of a Cu-TSVs process.


"With these tests, we have demonstrated that our technology allows designing and fabricating fully functional 3D SIC chips. We are now ready to accept reference test circuits from our industry partners," commented Eric Beyne, IMEC Scientific Director for 3D Technologies. "This will enable the industry to gain early insight and experience with 3D SIC design, using their own designs".

For stacking purposes, the top die was thinned down to 25µm and bonded to the landing die by Cu-Cu thermo-compression. IMEC noted that extensive tests confirmed that the performance of the circuits does not degrade with adding Cu TSVs and stacking. IMEC now plans to migrate the process to its 300mm platform.

Image: IMEC: Test-chip taped for assessing design rules and models for 3D-SIC technology.

IMEC: Test-chip taped for assessing design rules and models for 3D-SIC technology.

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