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IMEC and AIXTRON demonstrate AlGaN/GaN structures on 200mm silicon wafers

03 June 2008 | By Síle Mc Mahon | News > Wafer Processing

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IMECIn joint development work, IMEC and AIXTRON have said that they have successfully deposited crack-free AlGaN/GaN structures onto 200mm Si(111) wafers. This is the first such demonstration, according to the development team. The aim is to reach full fabrication of low-cost GaN power devices for high-efficiency/high-power systems beyond the silicon limits. 

"The demonstration of GaN growth on 200mm Si wafers is an important step towards processing GaN devices on large Si wafers", said Marianne Germain, Program Manager of IMEC's Efficient Power program. "There is a strong demand for GaN-based solid-state switching devices in the field of power conversion. However, bringing GaN devices to a level acceptable for most applications requires a drastic reduction in the cost of this technology. And that is only possible by processing on large-diameter Si wafers. 150mm, and then 200mm are the minimum wafer sizes we need to fully leverage today's silicon processing capabilities."

Further work is required such as wafer bow, which is in the range of 100µm; but IMEC believes that an optimized buffer can reduce this bow drastically, enabling further processing.

The AlGaN/GaN heterostructures were created using a standard layer stack, that had previously worked on 100 and 150mm Si(111) substrates. Firstly, an AlN layer was deposited onto the Si substrate, followed by an AlGaN buffer that creates a compressive stress in the 1-micron-thick GaN top layer. The stack was finished with a 20nm thin AlGaN (26% Al) layer and capped with a 2nm GaN layer. Thickness uniformity of the different layers was found to be well below 1% over the full 200mm wafers (5mm EE).

The AlGaN and GaN layers were grown in AIXTRON’s application laboratory on the 300mm CRIUS metal-organic chemical-vapor-phase epitaxy (MOVPE) reactor. The 200mm wafers were said to be custom-made by MEMC Electronic Materials, using the Czochralski growth (CZ) method.

"We aim to further develop the growth process and to qualify the wafers to be compatible with Si-CMOS process," noted Germain.

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Caption: Thickness uniformity map of a 1µm GaN layer deposited on 200mm Si(111) using an AlN/AlGaN buffer. The average thickness measured in-situ is 1008nm (? = 0.5%) for the full wafer excluding a 5mm edge.

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